1. Field of the Invention
The present invention relates to expansion boards in computer systems, and more particularly to a circuit that distinguishes between different expansion bus types to allow expansion boards to take advantage of certain features offered by different expansion buses.
2. Description of the Prior Art
In 1981, International Business Machines Corp. (IBM) introduced its personal computer, the IBM PC. The bus architecture in the IBM PC included a 20 bit address bus and a 16 bit data bus and utilized a timing standard that was designed for the relatively slow memory devices available at that time. The twenty address lines were referred to as the system address lines SA&lt;19-0&gt;.
After the introduction of the IBM PC, memory component capabilities and speeds increased dramatically, resulting in faster memory access times. The original SA&lt;19-0&gt; address lines used in the IBM PC architecture incorporated a timing standard that was too slow to take advantage of these advances in memory speeds. Therefore, an extended version of the bus architecture used in the IBM PC was introduced in a new personal computer from IBM called the PC/AT. The bus architecture in the PC/AT included a new set of address lines, the latched address lines LA&lt;23-17&gt;, which incorporated a timing standard that took advantage of the faster memory devices. The bus interface standard used in the IBM PC/AT has generally become known as the Industry Standard Architecture (ISA).
As is inevitable in the computer and electronics industry, capabilities of the various components, including memory components and microprocessor performance, continued to increase. In order to take full advantage of these developments, an extended version of the ISA was developed called the Extended Industry Standard Architecture (EISA). EISA includes a 32-bit address bus, a 32-bit data bus, and full backwards compatibility with ISA devices and software. The EISA connector was designed to be able to receive both ISA and EISA expansion boards. When an ISA expansion board is inserted into an EISA connector, the ISA board only connects with the ISA signal lines in the EISA bus. The EISA lines remain unconnected. When an EISA expansion board is inserted into an EISA connector slot, the EISA board connects with all of the signals forming the EISA bus, including both ISA and EISA signals.
The EISA bus specification includes features that can be used by expansion boards which do not utilize the full EISA bus connector, i.e., ISA expansion boards. These features include automatic system configuration and faster DMA transfer rates. Automatic system configuration provides automatic configuration of system resources and expansion boards through software. Faster DMA transfer rates are provided by certain DMA cycle types available on the EISA bus. For more information on these features, please see the EISA specification Version 3.1 provided in U.S. Pat. No. 5,101,492 filed Sep. 3, 1989, issued Mar. 31, 1992 and entitled "Data Redundancy and Recovery Protection" by Schultz, et al., which fully explains the requirements of an EISA system and is hereby incorporated by reference.
Since these features do not require the full EISA connector, i.e., can be used with only ISA signals, it has been desirable to include logic on ISA boards which allow ISA boards to take advantage of these features. In this manner, ISA boards can perform as ISA boards in ISA systems, and can use the above-mentioned features in EISA systems. However, when the expansion board is in an ISA system, use of the EISA features must be disabled. Otherwise, the ISA board would attempt to use these EISA features in the ISA system, resulting in probably erroneous operation. When the ISA board is installed in an EISA system, the ISA board must be set to "EISA mode" to allow the board to take advantage of the EISA features discussed above. Therefore, an ISA expansion board which is designed to take advantage of the above EISA features when it is in an EISA system must be informed as to whether it is in an ISA system or an EISA system.
Currently, ISA boards that are designed to take advantage of EISA features included a jumper with two positions indicating whether the board is in an ISA or EISA system. One disadvantage to this approach is that a jumper is required to put the board in EISA mode. The EISA architecture was designed to be a jumperless architecture, and hence requiring a jumper to place an ISA board into EISA mode is undesirable. This also creates more difficulty for the end user. If the user should forget or be unaware to switch the jumper when moving the board to a different system, then the I/O board would not operate properly. Therefore, an improved method and apparatus is desired to inform an ISA board as to whether it is connected to an ISA or EISA system.
Background on the development of I/O addressing in the EISA architecture is deemed appropriate. When the specification for the EISA bus was being formulated, a major consideration was to retain compatibility with prior ISA devices. This consideration was important because a user generally desires to upgrade and improve input/output subsystems without replacing the user's existing application programs or present input/output devices and controllers. Both existing applications programs and present input/output devices represent a significant investment in time and money to the user. As discussed below, certain limitations in the ISA standard presented problems in providing additional I/O address space for EISA circuit boards while retaining compatibility with the ISA standard.
The Industry Standard Architecture has evolved through a complicated expansion path resulting from the need to overcome limitations of earlier processors, operating systems and designs. A limitation of the ISA bus standard was that the standard limited addressing input/output space of circuit boards to ten bits of address space. One fourth of that space (the condition where the two most significant bits are zero) was reserved for use by the system board and was not available to the input/output circuit boards. Hence, only a very limited amount of input/output space was available. Over time and based on usage, portions of this address area had been reserved for particular input/output devices and their controllers and thus this space was saturated by existing input/output devices. Since there was insufficient address space to allocate to new advanced input/output devices and controllers, a method was needed to provide I/O space for new EISA circuit boards while keeping the old address map unchanged.
Therefore, a principal difficulty was that, under the ISA architecture, ISA expansion boards knew when they were addressed by decoding no more than ten bits of an input/output address word communicated through the ISA bus. The address locations within the address space allocated to the board were fixed in the circuit board, i.e., the circuit board determined whether it was addressed when some upper bit subset of the input/output address word corresponded with a fixed code. Therefore it was not possible to simply allocate more bits to the input/output address space to extend the addressing space available. Existing boards did not decode those higher bits spaces and thus existing boards would interfere with the new boards attempting to utilize this extended input/output space.
Therefore, the EISA architecture was developed with a technique referred to as EISA slot-specific I/O addressing. This addressing system allows a computer system to use existing circuit boards and yet provides additional addressing space for new circuit boards fully utilizing the addressing system. EISA slot-specific I/O addressing utilizes a slot specific signal referred to as AENx wherein "x" refers to the slot number. When the respective AENx signal is negated low to a board, then the respective I/O board may respond to addresses and I/O commands on the bus. The AENx signal is asserted high to all other option slots to disable I/O accesses during an access to a particular slot-specific I/O address range. The AENx signal is asserted high during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. A signal referred to as BALE is an ISA signal that indicates that a valid address is present on the address lines. The BALE signal is high during a DMA or a 16 bit ISA bus master operation.
The EISA slot-specific addressing system works generally as follows. Previously, when the A8 and A9 address bits were zero during an input/output space operation, system board devices were addressed. In the EISA slot-specific addressing system, when these bits are both zero, the A12-A15 bits are used to determine the specific slot or location which is being addressed. The zero slot is assigned to the system board for compatibility reasons. The remaining slots 1-15 are available for EISA expansion boards. When the A8 and A9 bits are zero during an input/output space operation and a respective slot is being addressed, its AENx line is negated low, with the individual AENx lines to each of the other slots being high to disable operation of any additional installed circuit boards.. In this manner, EISA expansion boards can be allocated I/O address space that does not conflict with current ISA expansion boards. Also, as previously mentioned, the BALE signal is negated during a slot-specific I/O cycle. To allow use of ISA boards, the EISA addressing system sets all of the AENx lines low if either the A 8 or A9 address bit is a one and an input/output space operation is occurring. Additionally, the AENx lines are low during memory space operations and high during direct memory access operations to conform to the ISA standard. For more information on the EISA slot-specific addressing system, please see U.S. Pat. No. 4,999,805 titled "Extended Input/Output Circuit Board Addressing System" by Culley et al., which is hereby incorporated by reference.